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i PEM Gb 4.2 Gb SDRAM-DDR2 Austin Semiconductor, Inc. AS4DDR264M65PBG1 64Mx64 DDR2 SDRAM w/ DUAL CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit
FEATURES
DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Extended Temp Package: * Proprietary Enchanced Die Stacked iPEM * 208 Plastic Ball Grid Array (PBGA), 16 x 23mm * 1.00mm ball pitch Differential data strobe (DQS, DQS#) per byte Internal, pipelined, double data rate architecture 4n-bit prefetch architecture DLL for alignment of DQ and DQS transitions with clock signal Eightinternal banks for concurrent operation (Per DDR2 SDRAM Die) Programmable Burst lengths: 4 or 8 Auto Refresh and Self Refresh Modes (I/T Version) On Die Termination (ODT) Adjustable data - output drive strength 1.8V 0.1V common core power and I/O supply Programmable CAS latency: 3, 4, 5, 6 or 7 Posted CAS additive latency: 0, 1, 2, 3, 4 or 5 Write latency = Read latency - 1* tCK Organized as 64M x 64 Weight: AS4DDR264M64PBG1 ~ 2.0 grams typical
NOTE: Self Refresh Mode available on Industrial and Enhanced temp. only
BENEFITS
58% Space Savings 49% I/O reduction vs Individual CSP approach Reduced part count Reduced trace lengths for lower parasitic capacitance Suitable for hi-reliability applications Upgradable to 128M x 64 density in future Pin / Function equivalent to White W3H64M64E-xSBx
FUNCTIONAL BLOCK DIAGRAM
Ax, BA0-2
ODT VRef VCC VCCQ VSS VSSQ VCCL VSSDL CSa\ WEa\ RASa\ CASa\ CKEa\
2 2 2 2 2 2 2 2
VCCQ VSSQ VCCL A VSSDL B CSb\ WEb\ RASb\ CASb\ CKEb\
VCCQ VSSQ VCCL VSSDL C
VCCQ VSSQ VCCL VSSDL D
2 2 2 2
2 2 2 2
ODT UDMx, UDMx LDMx UDSQx,UDSQx\ LDSQx, LDSQx\ CKx,CKx\ A
DQ0-15 B
DQ16-31 C
DQ32-47 D
DQ48-63
Austin Semiconductor, Inc.
AS4DDR264M65PBG1 Rev. 0.5 06/08
Austin, Texas
512.339.1188
www.austinsemiconductor.com
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i PEM Gb 4.2 Gb SDRAM-DDR2 Austin Semiconductor, Inc. AS4DDR264M65PBG1
SDRAM-DDRII Pinout Top View
Rev. A, 5/08, 208BGA-1.00MM PITCH - X64, DCB
1 A B C D E F G H J K L Vcc Vss DQ35 DQ52 LDM3 DQ38 UDM3 Vcc Vss Vcc 2 Vcc Vss NC DQ51 DQ36 LDM2 DQ54 DQ44 A6 A0 A2 3 Vss NC NC WEb\ DQ33 DQ49 DQ60 DQ41 A10 A11 A4 4 Vcc NC NC CKEb NC DQ43 DQ57 DQ46 A9 Vcc A8 DQ15 DQ24 DQ26 LDQS0 DQ21 DQ2 NC Vcc 4 5 Vcc NC NC NC BA2 DQ59 UDM2 DQ62 Vcc Vss Vcc UDQS0\ DQ31 DQ23 DQ7 DQ18 RASa\ CSa\ Vcc 5 6 Vss NC CASb\ NC NC NC Vss Vcc Vss Vref Vss Vcc Vss ODT NC NC CASa\ NC Vss 6 7 Vcc CSb\ RASb\ DQ50 DQ39 DQ55 DQ63 UDQS2\ Vcc Vss Vcc DQ30 UDM0 DQ27 NC NC NC NC Vcc 7 8 Vcc NC DQ34 DQ53 LDQS2 DQ58 DQ56 DQ47 A3 Vcc BA0 DQ14 DQ25 DQ11 NC CKEa NC NC Vcc 8 9 Vss NC CK3 DQ37 LDQS3 DQ42 DQ40 10 Vcc Vss CK3\ CK2\ DQ48 11 Vss Vcc Vss CK2 DQ32 A B C D E
LDQS2\ LDQS3\ F DQ61 DQ45 G
UDQS2 UDQS3 UDQS3\ H A12 A1 A5 DQ9 DQ28 DQ17 DQ1 WEa\ NC NC Vss 9 RFU BA1 A7 DQ12 DQ22 LDM0 DQ4 DQ19 NC Vss Vcc 10 Vcc Vss Vcc J K L
M UDQS1\ UDQS1 UDQS0 N DQ13 DQ29 DQ8 DQ10 LDQS1 DQ5 CK1 NC Vss 3
UDM1 M DQ6 N
P LDQS1\ LDQS0\ R T U V W DQ0 CK0 Vss Vcc Vss 1 DQ16 CK0\ CK1\ Vss Vcc 2
LDM1 p DQ20 R DQ3 Vss Vcc Vss 11 T U V W
Ground CNTRL Data I/O
Array Power Level REF.
UNPOPULATED NC
Address RFU
AS4DDR264M65PBG1 Rev. 0.5 06/08
Austin Semiconductor, Inc.
Austin, Texas
512.339.1188
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i PEM Gb 4.2 Gb SDRAM-DDR2 Austin Semiconductor, Inc. AS4DDR264M65PBG1
BGA Locations P6 C9,C10,D10,D11,T1,T2, U2,U3 T8, D4 V5, B7 U5, C7 U6, C6 T9, D3 G5,H1,M11,N7 F1,F2,P10,P11 H9,H10,M2,M3 H7,H11,M1,M5 E8,E9,R3,R4 F10,F11,P1,P2 J2,J3,J4,J8,J9, K2, K3,K9,L2,L3,L4,L9,L10 Symbol ODT CKx, CKx\ CKE CS\ RASx\ CASx\ WE\ UDMx LDMx UDQSx UDQSx\ LDQSx LDQSx\ Ax Type CNTL Input CNTL Input CNTL Input CNTL Input CNTL Input CNTL Input CNTL Input CNTL Input CNTL Input CNTL Input CNTL Input CNTL Input CNTL Input Input Description On-Die-Termination: Registered High enables on data bus termination Differential input clocks, one set for each x16bits Clock enable which activates all on silicon clocking circuitry Chip Selects, one for each 16 bits of the data bus width Command input which along with CAS\, WE\ and CS\ define operations Command input which along with RAS\, WE\ and CS\ define operations Command input which along with RAS\, CAS\ and CS\ define operations One Data Mask cntl. for each upper 8 bits of a x16 word One Data Mask cntl. For each lower 8 bits of a x16 word Data Strobe input for upper byte of each x16 word Differential input of UDQSx, only used when Differential DQS mode is enabled Data Strobe input for lower byte of each x16 word Differential input of LDQSx, only used when Differential DQS mode is enabled Array Address inputs providing ROW addresses for Active commands, and the column address and auto precharge bit (A10) for READ/WRITE commands
J10 RFU Future Input L8,K10,E5 BA0,BA1,BA2 Input C8,D1,D2,D7,D8,D9,E1, DQx Input/Output E2,E3,E7,E10,E11,F3, F4,F5,F7,F8,F9,G1,G2, G3,G4,G7,G8,G9,G10, G11,H2,H3,H4,H5,H8, M4,M7,M8,M9,M10,N1, N2,N3,N4,N5,N8,N9, N10,N11,P3,P4,P5,P7, P8,P9,R1,R2,R5,R9, R10,R11,T3,T4,T5, T10,T11,U4 H6 Vref Supply A2,A4,A5,A7,A8,A10, VCC Supply B1,B11,H6,J1,J5,J7,J11, K4,K8,L1,L5,L7,L11,M6, V1,V11,W2,W4,W5, W7,W8,W10 A3,A6,A9,A11,B2,B10, VSS Supply C1,C11,G6,J6,K1,K5, K7,K11,L6,N6,U1,U11, V2,V10,W1,W3,W6, W9,W11 B3,B4,B5,B6,B8,B9, NC C2,C3,C4,C5,D5,D6,E4, E6, F6, R6,R7,R8, T6,T7,U7,U8,U9,U10, V3,V4,V6,V7,V8,V9 A1 UNPOPULATED
Bank Address inputs Data bidirectional input/Output pins
SSTL_18 Voltage Reference Core Power Supply
Core Ground return
No connection
Unpopulated ball matrix location (location registration aid)
AS4DDR264M65PBG1 Rev. 0.5 06/08
Austin Semiconductor, Inc.
Austin, Texas
512.339.1188
www.austinsemiconductor.com
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i PEM Gb 4.2 Gb SDRAM-DDR2 Austin Semiconductor, Inc. AS4DDR264M65PBG1
DESCRIPTION
The 4.2Gb DDR2 SDRAM, a high-speed CMOS, dynamic random-access memory containing 4,294,967,296 bits. Each of the four chips in the MCP are internally configured as 8-bank DRAM. The block diagram of the device is shown in Figure 2. Ball assignments and are shown in Figure 3. The 4.2Gb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the x64 DDR2 SDRAM effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. There are strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#). The MCP DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR2 SDRAM provides for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read, or a burst write of eight with another write. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAMs, the pipelined, multibank architecture of DDR2 SDRAMs allows for concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength outputs are SSTL_18compatible.
GENERAL NOTES
* The functionality and the timing specifications discussed in this data sheet are for the DLLenabled mode of operation. * Throughout the data sheet, the various figures and text refer to DQs as DQ. The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, each chip is divided into 2 bytes, the lower byte and upper byte. For the lower byte (DQ0 CDQ7), DM refers to LDM and DQS refers to LDQS. For the upper byte (DQ8 CDQ15), DM refers to UDM and DQS refers to UDQS. * Complete functionality is described throughout the document and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. * Any specific requirement takes precedence over a general statement.
INITIALIZATION
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. The following sequence is required for power up and initialization and is shown in Figure 4 on page 5.
AS4DDR264M65PBG1 Rev. 0.5 06/08
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i PEM Gb 4.2 Gb SDRAM-DDR2 Austin Semiconductor, Inc. AS4DDR264M65PBG1
FIGURE 4 - POWER-UP AND INITIALIZATION
Notes appear on page 7
VDD VDDL VDDQ
VTT1 VREF
T0 tCK Ta0 Tb0 Tc0 Td0 Te0 Tf0 Tg0 Th0 Ti0 Tj0 Tk0 Tl0 Tm0
t VTD1
CK# CK
tCL tCL
LVCMOS 2 SSTL_18 2 CKE LOW LEVEL LOW LEVEL
ODT
Comman d
3
NOP4
PRE
LM 5
LM 6
LM 7
LM 8
9 PRE
10 REF
REF
LM 11
LM 12
LM 13
Vali d16
DM
15
3 Address
A10 = 1
Code
Code
Code
Code
A10 = 1
Code
Code
Code
Vali d
DQS
15 15
High-Z High-Z High-Z
DQ
RTT
T = 200s (MIN) Power-up: VDD and stable clo ck (CK, CK#)
T = 400ns (MIN) 16
t RPA EMR(2)
t MRD
t MRD EMR(3) EMR
t MRD
t MRD
t RPA
t RF C
t RF C See note 17
t MRD
t MRD EMR with OCD exit
t MRD
MR without DLL RE SET MR with DLL RE SET
EMR with OCD default
200 cycles of CK are re quire d before a READ comman d can be issued.
Normal operation
Indicates a break in time s cale
Don 't care
AS4DDR264M65PBG1 Rev. 0.5 06/08
Austin Semiconductor, Inc.
Austin, Texas
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i PEM Gb 4.2 Gb SDRAM-DDR2 Austin Semiconductor, Inc. AS4DDR264M65PBG1
NOTES: 1. Applying power; if CKE is maintained below 0.2 x VCCQ, outputs remain disabled. To guarantee RTT (ODT resistance) is off, VREF must be valid and a low level must be applied to the ODT ball (all other inputs may be undefined, I/Os and outputs must be less than VCCQ during voltage ramp time to avoid DDR2 SDRAM device latch-up). VTT is not applied directly to the device; however, tVTD should be 0 to avoid device latch-up. At least one of the following two sets of conditions (A or B) must be met to obtain a stable supply state (stable supply defined as VCC, VCCQ,VREF, and VTT are between their minimum and maximum values as stated in DC Operating Conditionstable): A. (single power source) The VCC voltage ramp from 300mV to VCC(MIN) must take no longer than 200ms; during the VCC voltage ramp, |VCC - VCCQ| < 0.3V. Once supply voltage ramping is complete (when VCCQ crosses VCC (MIN), DC Operating Conditions table specifications apply. * VCC, VCCQ are driven from a single power converter output * VTT is limited to 0.95V MAX * VREF tracks VCCQ/2; VREF must be within 3V with respect to VCCQ/2 during supply ramp time. * VCCQ > VREF at all times B. (multiple power sources) VCC e" VCCQ must be maintained during supply voltage ramping, for both AC and DC levels, until supply voltage ramping completes (VCCQ crosses VCC [MIN]). Once supply voltage ramping is complete, DC Operating Conditions table specifications apply. * Apply VCC before or at the same time as VCCQ; VCC voltage ramp time must be < 200ms from when VCC ramps from 300mV to VCC (MIN) * Apply VCCQ before or at the same time as VTT; the VCCQ voltage ramp time from when VCC (MIN) is achieved to when VCCQ (MIN) is achieved must be < 500ms; while VCC is ramping, current can be supplied from VCC through the device to VCCQ * VREF must track VCCQ/2, VREF must be within 0.3V with respect to VCCQ/2 during supply ramp time; VCCQ > VREF must be met at all times * Apply VTT; The VTT voltage ramp time from when VCCQ (MIN) is achieved to when VTT (MIN) is achieved must be no greater than 500ms 2. CKE requires LVCMOS input levels prior to state T0 to ensure DQs are High-Z during device power-up prior to VREF being stable. After state T0, CKE is required to have SSTL_18 input levels. Once CKE transitions to a high level, it must stay HIGH for the duration of the initialization sequence. 3. A10 = PRECHARGE ALL, CODE = desired values for mode registers (bank addresses are required to be decoded). 4. For a minimum of 200s after stable power and clock (CK, CK#), apply NOP or DESELECT commands, then take CKE HIGH. 5. Issue a LOAD MODE command to the EMR(2). To issue an EMR(2) command, provide LOW to BA0, and provide HIGH to BA1; set register E7 to "0" or "1" to select appropriate self refresh rate; remaining EMR(2) bits must be "0" (see "Extended Mode Register 2 (EMR2)" on page 84 for all EMR(2) requirements). 6. Issue a LOAD MODE command to the EMR(3). To issue an EMR(3) command, provide HIGH to BA0 and BA1; remaining EMR(3) bits must be "0." See "Extended Mode Register 3 (EMR 3)" on page 13 for all EMR(3) requirements. 7. Issue a LOAD MODE command to the EMR to enable DLL. To issue a DLL ENABLE command, provide LOW to BA1 and A0; provide HIGH to BA0; bits E7, E8, and E9 can be set to "0" or "1;" Austin recommends setting them to "0;" remaining EMR bits must be "0. "See "Extended Mode Register (EMR)" on page 10 for all EMR requirements. 8. Issue a LOAD MODE command to the MR for DLL RESET. 200 cycles of clock input is required to lock the DLL. To issue a DLL RESET, provide HIGH to A8 and provide LOW to BA1 and BA0; CKE must be HIGH the entire time the DLL is resetting; remaining MR bits must be "0." See "Mode Register (MR)" on page 7 for all MR requirements. 9. Issue PRECHARGE ALL command. 10. Issue two or more REFRESH commands. 11. Issue a LOAD MODE command to the MR with LOW to A8 to initialize device operation (that is, to program operating parameters without resetting the DLL). To access the MR, set BA0 and BA1 LOW; remaining MR bits must be set to desired settings. See "Mode Register (MR)" on page 7 for all MR requirements. 12. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8, and E9 to "1," and then setting all other desired parameters. To access the EMR, set BA0 LOW and BA1 HIGH (see "Extended Mode Register (EMR)" on page 10 for all EMR requirements). 13. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and E9 to "0," and then setting all other desired parameters. To access the extended mode registers, EMR, set BA0 LOW and BA1 HIGH for all EMR requirements. 14. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles after the DLL RESET at Tf0. 15. DM represents UDM, LDM collectively for each die x16 configuration. DQS represents UDQS, USQS, LDQS, LDQS for each die x16 configuration. DQ represents DQ0-DQ15 for each die x16 configuration. 16. Wait a minimum of 400ns then issue a PRECHARGE ALL command.
AS4DDR264M65PBG1 Rev. 0.5 06/08
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i PEM Gb 4.2 Gb SDRAM-DDR2 Austin Semiconductor, Inc. AS4DDR264M65PBG1
MODE REGISTER (MR)
The mode register is used to define the specific mode of operation of the DDR2 SDRAM. This definition includes the selection of a burst length, burst type, CL, operating mode, DLL RESET, write recovery, and power-down mode, as shown in Figure 5. Contents of the mode register can be altered by re-executing the LOAD MODE (LM) command. If the user chooses to modify only a subset of the MR variables, all variables (M0-M14) must be programmed when the command is issued. The mode register is programmed via the LM command (bits BA2-BA0 = 0, 0,0) and other bits (M13-M0) will retain the stored information until it is programmed again or the device loses power (except for bit M8, which is selfclearing). Reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly. The LM command can only be issued (or reissued) when all banks are in the precharged state (idle state) and no bursts are in progress. The controller must wait the specified time tMRD before initiating any subsequent operations such as an ACTIVE command. Violating either of these requirements will result in unspecified operation.
FIGURE 5 - MODE REGISTER (MR) DEFINITION
2 1 1 2 BA2 BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
16 15 14 n 12 11 10 1 0 MR WR 0 PD
9
8
7
6
5
4
3
2
1
0
Mode Register (Mx)
DLL TM CAS# Latency BT Burst Length
M12 0 1
PD Mode Fast exit (normal) Slow exit (low power)
M7 Mode 0 Normal 1 Test
M2 M1 M0 Burst Length 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Reserved Reserved 4 8 Reserved Reserved Reserved Reserved
M8 DLL Reset 0 1 No Yes
M11 M10 M9 0 0 0 0 1 1 1 1 M15 M16 0 0 1 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Write Recovery Reserved 2 3 4 5 6 7 8 M6 M5 M4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 M3 0 1
Burst Type Sequential Interleaved
CAS Latency (CL) Reserved Reserved Reserved 3 4 5 6 7
BURST LENGTH
Burst length is defined by bits M0-M3, as shown in Figure 5. Read and write accesses to the DDR2 SDRAM are burstoriented, with the burst length being programmable to either four or eight. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A2-Ai when BL = 4 and by A3-Ai when BL = 8 (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts.
Mode Register Definition Mode register (MR) Extended mode register (EMR) Extended mode register (EMR2) Extended mode register (EMR3)
Notes: 1.A13 Not used on this part, and must be programmed to `0' on this part. 2.BA2 must be programmed to "0" and is reserved for future use.
BURST TYPE
Accesses within a given burst may be programmed to be either sequential or interleaved. The burst type is selected via bit M3, as shown in Figure 5. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 2. DDR2 SDRAM supports 4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode, full interleave address ordering is supported; however, sequential address ordering is nibble-based.
AS4DDR264M65PBG1 Rev. 0.5 06/08
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TABLE 2 - BURST DEFINITION
Burst Length Starting Column Address A1 0 4 0 1 1 A2 0 0 0 8 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 Order of Accesses Within a Burst Type = Sequential Type = Interleaved
DLL RESET
DLL RESET is defined by bit M8, as shown in Figure 5. Programming bit M8 to "1" will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a value of "0" after the DLL RESET function has been issued. Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.
WRITE RECOVERY
Write recovery (WR) time is defined by bits M9-M11, as shown in Figure 5. The WR register is used by the DDR2 SDRAM during WRITE with auto precharge operation. During WRITE with auto precharge operation, the DDR2 SDRAM delays the internal auto precharge operation by WR clocks (programmed in bits M9-M11) from the last data burst. WR values of 2, 3, 4, 5, 6 or 7 clocks may be used for programming bits M9-M11. The user is required to program the value of WR, which is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up a non integer value to the next integer; WR [cycles] = tWR [ns] / tCK [ns]. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
NOTES: 1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the starting column within the block. 2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the starting column within the block. 3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the starting column within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
OPERATING MODE
The normal operating mode is selected by issuing a command with bit M7 set to "0" and all other bits set to the desired values, as shown in Figure 5. When bit M7 is "1," no other bits of the mode register are programmed. Programming bit M7 to "1" places the DDR2 SDRAM into a test mode that is only used by the manufacturer and should not be used. No operation or functionality is guaranteed if M7 bit is "1."
POWER-DOWN MODE
Active power-down (PD) mode is defined by bit M12, as shown in Figure 5. PD mode allows the user to determine the active power-down mode, which determines performance versus power savings. PD mode bit M12 does not apply to precharge PD mode. When bit M12 = 0, standard active PD mode or "fast-exit" active PD mode is enabled. The tXARD parameter is used for fast-exit active PD exit timing. The DLL is expected to be enabled and running during this mode. When bit M12 = 1, a lower-power active PD mode or "slowexit" active PD mode is enabled. The tXARD parameter is used for slow-exit active PD exit timing. The DLL can be enabled, but "frozen" during active PD mode since the exit-to-READ command timing is relaxed. The power difference expected between PD normal and PD low-power mode is defined in the ICC table.
AS4DDR264M65PBG1 Rev. 0.5 06/08
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CAS LATENCY (CL)
The CAS latency (CL) is defined by bits M4-M6, as shown in Figure 5. CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The CL can be set to 3, 4, 5, 6 or 7 clocks, depending on the speed grade option being used. DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be used as unknown operation or incompatibility with future versions may result. DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This feature allows the READ command to be issued prior to tRCD (MIN) by delaying the internal command to the DDR2 SDRAM by AL clocks. Examples of CL = 3 and CL = 4 are shown in Figure 6; both assume AL = 0. If a READ command is registered at clock edge n, and the CL is m clocks, the data will be available nominally coincident with clock edge n+m (this assumes AL = 0).
FIGURE 6 - CAS LATENCY (CL)
T0 CK# CK Command READ
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
NOP
NOP
NOP
DQS, DQS#
DQ CL = 3 (AL = 0)
DO n
DO n+1
DO n+2
DO n+3
T0 CK# CK Command READ
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
NOP
NOP
NOP
DQS, DQS#
DQ CL = 4 (AL = 0)
DO n
DO n+1
DO n+2
DO n+3
Transitioning data
Don't care
Notes:
1. BL = 4. 2. Posted CAS# additive latency (AL) = 0. 3. Shown with nominal t AC, t DQSCK, and t DQSQ.
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EXTENDED MODE REGISTER (EMR)
The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, on die termination (ODT) (RTT), posted AL, off-chip driver impedance calibration (OCD), DQS# enable/disable, RDQS/RDQS# enable/disable, and output disable/enable. These functions are controlled via the bits shown in Figure 7. The EMR is programmed via the LOAD MODE (LM) command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly. The EMR must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could esult in unspecified operation.
FIGURE 7 - EXTENDED MODE REGISTER DEFINITION
1 2 2 BA2 3 BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
16 0
8765432 10 15 14 n 12 11 10 9 MRS 0 2 Out RDQS DQS# OCD Program RTT Posted CAS# R ODS DLL TT
Extended mode register (Ex)
E12 0 1
Outputs Enabled Disabled
E0 E6 E2 RTT (Nominal) 00 01 10 11 RTT disabled 75 150 50 E1 0 1 0 1
DLL Enable Enable (normal) Disable (test/debug)
E11 RDQS Enable 0 1 No Yes
Output Drive Strength Full (100%) Reduced (40-60%)
4
E10 DQS# Enable 0 1 Enable Disable
E5 E4 E3 Posted CAS# Additive Latency (AL) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 Reserved
E9 E8 E7 OCD Operation 0 0 0 1 1 E15 E14 0 0 1 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 OCD exit Reserved Reserved Reserved Enable OCD defaults
Mode Register Set Mode register (MR) Extended mode register (EMR) Extended mode register (EMR2) Extended mode register (EMR3)
Notes: 1.During initialization, all three bits must be set to "1" for OCD default state, then must be set to "0" before initialization is finished, as detailed in the initialization procedure. 2.E13 (A13) must be programmed to "0" and is reserved for future use. 3.E16 must be programmed to "0" and is reserved for future use. 4.Not all AL options are supported in any individual speed grade.
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DLL ENABLE/DISABLE
The DLL may be enabled or disabled by programming bit E0 during the LM command, as shown in Figure 7. The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debugging or evaluation. Enabling the DLL should always be followed by resetting the DLL using an LM command. The DLL is automatically disabled when entering SELF REFRESH operation and is automatically re-enabled and reset upon exit of SELF REFRESH operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a READ command can be issued, to allow time for the internal clock to synchronize with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.
OUTPUT ENABLE/DISABLE
The OUTPUT ENABLE function is defined by bit E12, as shown in Figure 7. When enabled (E12 = 0), all outputs (DQs, DQS, DQS#, RDQS, RDQS#) function normally. When disabled (E12 = 1), all DDR2 SDRAM outputs (DQs, DQS, DQS#, RDQS, RDQS#) are disabled, thus removing output buffer current. The output disable feature is intended to be used during ICC characterization of read current.
ON-DIE TERMINATION (ODT)
ODT effective resistance, RTT (EFF), is defined by bits E2 and E6 of the EMR, as shown in Figure 7. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DDR2 SDRAM controller to independently turn on/off ODT for any or all devices. RTT effective resistance values of 50, 75, and 150 are selectable and apply to each DQ, DQS/DQS#, RDQS/ RDQS#, UDQS/UDQS#, LDQS/ LDQS#, DM, and UDM/ LDM signals. Bits (E6, E2) determine what ODT resistance is enabled by turning on/off "sw1," "sw2," or "sw3." The ODT effective resistance value is elected by enabling switch "sw1," which enables all R1 values that are 150 each, enabling an effective resistance of 75 (RTT2(EFF) = R2/2). Similarly, if "sw2" is enabled, all R2 values that are 300 each, enable an effective ODT resistance of 150 (RTT2(EFF) = R2/2). Switch "sw3" enables R1 values of 100 enabling effective resistance of 50 Reserved states should not be used, as unknown operation or incompatibility with future versions may result. The ODT control ball is used to determine when RTT(EFF) is turned on and off, assuming ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and ODT input ball are only used during active, active power-down (both fast-exit and slow-exit modes), and precharge powerdown modes of operation. ODT must be turned off prior to entering self refresh. During power-up and initialization of the DDR2 SDRAM, ODT should be disabled until issuing the EMR command to enable the ODT feature, at which point the ODT ball will determine the RTT(EFF) value. Any time the EMR enables the ODT function, ODT may not be driven HIGH until eight clocks after the EMR has been enabled. See "ODT Timing" section for ODT timing diagrams.
OUTPUT DRIVE STRENGTH
The output drive strength is defined by bit E1, as shown in Figure 7. The normal drive strength for all outputs are specified to be SSTL_18. Programming bit E1 = 0 selects normal (full strength) drive strength for all outputs. Selecting a reduced drive strength option (E1 = 1) will reduce all outputs to approximately 45-60 percent of the SSTL_18 drive strength. This option is intended for the support of lighter load and/or point-to-point environments.
DQS# ENABLE/DISABLE
The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is the complement of the differential data strobe pair DQS/ DQS#. When disabled (E10 = 1), DQS is used in a single ended mode and the DQS# ball is disabled. When disabled, DQS# should be left floating. This function is also used to enable/disable RDQS#. If RDQS is enabled (E11 = 1) and DQS# is enabled (E10 = 0), then both DQS# and RDQS# will be enabled.
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POSTED CAS ADDITIVE LATENCY (AL)
Posted CAS additive latency (AL) is supported to make the command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. Bits E3-E5 define the value of AL, as shown in Figure 7. Bits E3-E5 allow the user to program the DDR2 SDRAM with an inverse AL of 0, 1, 2, 3, 4, 5 or 6 clocks. Reserved states should not be used as unknown operation or incompatibility with future versions may result. In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued prior to tR CD (MIN) with the requirement that AL = tRCD (MIN). A typical application using this feature would set AL = tRCD (MIN) - 1x tCK. The READ or WRITE command is held for the time of the AL before it is issued internally to the DDR2 SDRAM device. RL is controlled by the sum of AL and CL; RL = AL+CL. Write latency (WL) is equal to RL minus one clock; WL = AL + CL - 1 x tCK.
FIGURE 8 - EXTENDED MODE REGISTER 2 (EMR2) DEFINITION
1 2 BA2 BA1 BA0 An 1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
A1 A0
Address bus
16 0
15 14 n MRS 0
12 11 00
10 9 8 7 6 0 0 SRT 0 0
5432 0000
1 0
0 0
Extended mode register (Ex)
E15 E14 0 0 1 1 0 1 0 1
Mode Register Set Mode register (MR) Extended mode register (EMR) Extended mode register (EMR2) Extended mode register (EMR3)
E7 0 1
SRT Enable 1X refresh rate (0C to 85C) 2X refresh rate (>85C)
Notes: 1.E16 bit (BA2) must be programmed to "0" and is reserved for future use. 2.Mode bits (En) with corresponding address balls (An) greater than A12 are reserved for future use and must be programmed to "0."
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FIGURE 9 - EXTENDED MODE REGISTER 3 (EMR3) DEFINITION
1 2 BA22 BA1 BA0 An1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
16 0
15 14 n MRS 0
12 11 0 0
10 0
9 0
8 0
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 0
Extended mode register (Ex)
E15 E14 0 0 1 1 0 1 0 1
Mode Register Set Mode register (MR) Extended mode register (EMR) Extended mode register (EMR2) Extended mode register (EMR3)
Notes: 1.Mode bits (En) with corresponding address balls (An) greater than A12 are reserved for future use and must be programmed to "0." 2.E16 (BA2) must be programmed to "0" on this device and is reserved for future use.
EXTENDED MODE REGISTER 2
The extended mode register 2 (EMR2) controls functions beyond those controlled by the mode register. Currently all bits in EMR2 are reserved, as shown in Figure 8. The EMR2 is programmed via the LM command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly. EMR2 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. EMR3 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specifi ed time tMRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation.
COMMAND TRUTH TABLES
The following tables provide a quick reference of DDR2 SDRAM available commands, including CKE power-down modes, and bank-to-bank commands.
EXTENDED MODE REGISTER 3
The extended mode register 3 (EMR3) controls functions beyond those controlled by the mode register. Currently, all bits in EMR3 are reserved, as shown in Figure 9. The EMR3 is programmed via the LM command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly.
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TABLE 3 - TRUTH TABLE - DDR2 COMMANDS
CKE Function LOAD MODE REFRESH SELF-REFRESH Entry SELF-REFRESH exit Single Bank Precharge All banks PRECHARGE Bank Activate WRITE WRITE with auto precharge READ READ with auto precharge NO OPERATION Device DESELECT POWER-DOWN entry Previous Cycle H H H L H H H H H H H H H H Current Cycle H H L H H H H H H H H X X L CS# L L L H L L L L L L L L L H H L H L RAS# L L L X H L L L L H H H H X X H X H CAS# L L L X H H H H H L L L H X X H X H WE# L H H X H L L L L L H H H X X H X H BA2 thru BA0 BA X X X X X BA BA BA BA BA X X X X X X X X Column Address Column Address Column Address Column Address X X X A12 A11 A10 OP CODE X X X L H ROW ADDRESS L H L L X X X Column Address Column Address Column Address Column Address X X X 4 2,3 2,3 2,3 2,3 X X X X X 7 2 A9-A0 Notes 2
POWER-DOWN exit
L
H
X
X
X
X
4
Note: 1. All DDR2-SDRAM commands are defined by staes of CS#, RAS#, CAS#, WE#, and CKE a the rising edge of the clock. 2. Bank addresses (BA) BA2-BA0 determine which bank is to be operated upon. BA during a LM command selects which mode register is programmed. 3. Burst reads or writes at BL=4 cannot be terminated or interrupted. 4. The power down mode does not perform any REFRESH operations. The duration of power down is therefore limited by the refresh requirements outlined in the AC parametric section. 5. The state of ODT does not effect the states described in this table. The ODT function is not available during self refresh. See "On Die Termination (ODT)" for details. 6. "X" means "H or L" (but a defined logic level) 7. Self refresh exit is asynchronous.
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DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in progress are not affected. A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to perform a NOP (CS# is LOW; RAS#, CAS#, and WE are HIGH). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.
LOAD MODE (LM)
The mode registers are loaded via inputs BA2-BA0, and A12-A0. BA2-BA0 determine which mode register will be programmed. See "Mode Register (MR)". The LM command can only be issued when all banks are idle, and a subsequent execute able command cannot be issued until tMRD is met.
FIGURE 10 - ACTIVE COMMAND
CK# CK CKE CS# RAS# CAS# WE#
Row
BANK/ROW ACTIVATION ACTIVE COMMAND
The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA2-BA0 inputs selects the bank, and the address provided on inputs A12-A0 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank.
ACTIVE OPERATION
Before any READ or WRITE commands can be issued to a bank within the DDR2 SDRAM, a row in that bank must be opened (activated), even when additive latency is used. This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. The same procedure is used to convert other specification limits from time units to clock cycles. For example, a tRCD (MIN) specification of 20ns with a 266 MHz clock (tCK = 3.75ns) results in 5.3 clocks, rounded up to 6.
ADDRESS BANK ADDRESS
Bank
DON'T CARE
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READ COMMAND
The READ command is used to initiate a burst read access to an active row. The value on the BA2-BA0 inputs selects the bank, and the address provided on inputs A0-i (where i = A9) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses.
FIGURE 11 - READ COMMAND
READ OPERATION
READ bursts are initiated with a READ command. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is automatically precharged at the completion of the burst. If auto precharge is disabled, the row will be left open after the completion of the burst. During READ bursts, the valid data-out element from the starting column address will be available READ latency (RL) clocks later. RL is defined as the sum of AL and CL; RL = AL + CL. The value for AL and CL are programmable via the MR and EMR commands, respectively. Each subsequent dataout element will be valid nominally at the next positive or negative clock edge (i.e., at the next crossing of CK and CK#). DQS/DQS# is driven by the DDR2 SDRAM along with output data. The initial LOW state on DQS and HIGH state on DQS# is known as the read preamble (tRPRE). The LOW state on DQS and HIGH state on DQS# coincident with the last dataout element is known as the read postamble (tRPST). Upon completion of a burst, assuming no other commands have been initiated, the DQ will go High-Z. Data from any READ burst may be concatenated with data from a subsequent READ command to provide a continuous flow of data. The first data element from the new burst follows the last element of a completed burst. The new READ command should be issued x cycles after the first READ command, where x equals BL / 2 cycles.
CK# CK CKE CS#
RAS# CAS# WE# ADDRESS CHARGE AUTO PRE
Col ENABLE A10 DISABLE
BANK ADDRESS
Bank
DON'T CARE
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WRITE COMMAND
The WRITE command is used to initiate a burst write access to an active row. The value on the BA2-BA0 inputs selects the bank, and the address provided on inputs A0-9 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. The time between the WRITE command and the fi rst rising DQS edge is WL tDQSS. Subsequent DQS positive rising edges are timed, relative to the associated clock edge, as tDQSS. tDQSS is specified with a relatively wide range (25 percent of one clock cycle). All of the WRITE diagrams show the nominal case, and where the two extreme cases (tDQSS [MIN] and tDQSS [MAX]) might not be intuitive, they have also been included. Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain High-Z and any additional input data will be ignored. Data for any WRITE burst may be concatenated with a subsequent WRITE command to provide continuous flow of input data. The fi rst data element from the new burst is applied after the last element of a completed burst. The new WRITE command should be issued x cycles after the first WRITE command, where x equals BL/2. DDR2 SDRAM supports concurrent auto precharge options, as shown in Table 4. DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4 operation. Once the BL = 4 WRITE command is registered, it must be allowed to complete the entire WRITE burst cycle. However, a WRITE (with auto precharge disabled) using BL = 8 operation might be interrupted and truncated ONLY by another WRITE burst as long as the interruption occurs on a 4-bit boundary, due to the 4n prefetch architecture of DDR2 SDRAM. WRITE burst BL = 8 operations may not to be interrupted or truncated with any command except another WRITE command. Data for any WRITE burst may be followed by a subsequent READ command. The number of clock cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is greater. Data for any WRITE burst may be followed by a subsequent PRECHARGE command. tWT starts at the end of the data burst, regardless of the data mask condition.
WRITE OPERATION
WRITE bursts are initiated with a WRITE command, as shown in Figure 12. DDR2 SDRAM uses WL equal to RL minus one clock cycle [WL = RL - 1CK = AL + (CL - 1CK)]. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and subsequent data elements will be registered on successive edges of DQS. The LOW state on DQS between the WRITE command and the first rising edge is known as the write preamble; the LOW state on DQS following the last data-in element is known as the write postamble.
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FIGURE 12 - WRITE COMMAND
CK# CK CKE CS# RAS# CAS# HIGH
WE#
ADDRESS
CA
EN AP
A10
DIS AP
BANK ADDRESS
BA
DON'T CARE
Note: CA = column address; BA = bank address; EN AP = enable auto precharge; and DIS AP = disable auto precharge.
TABLE 4 - WRITE USING CONCURRENT AUTO PRECHARGE
From Command (Bank n ) WRITE with Auto Precharge
Minimum Delay (With Concurrent Auto Precharge) (CL-1) + (BL/2) + tWTR READ OR READ w/ AP WRITE OR WRITE w/ AP (BL/2) PRECHARGE or ACTIVE 1 To Command (Bank m )
Units
t t
CK CK t CK
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PRECHARGE COMMAND
The PRECHARGE command, illustrated in Figure 13, is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row activation a specified time (tRP) after the PRECHARGE command is issued, except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. However, the precharge period will be determined by the last PRECHARGE command issued to the bank.
FIGURE 13 - PRECHARGE COMMAND
CK# CK CKE HIGH CS#
RAS# CAS# WE# ADDRESS
ALL BANKS
PRECHARGE OPERATION
Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA2-BA0 select the bank. Otherwise BA2-BA0 are treated as "Don't Care." When all banks are to be precharged, inputs BA2-BA0 are treated as "Don't Care."
A10
ONE BANK
BA2, BA0 BA Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands DON'T CARE being issued to that bank. tRPA timing applies when the PRECHARGE (ALL) command is issued, regardless of the Note: BA = bank address (if A10 is LOW; otherwise "Don't Care"). number of banks already open or closed. If a single-bank PRECHARGE command is issued, tRP timing applies. issued). The differential clock should remain stable and meet tCKE specifications at least 1 x tCK after entering self refresh mode. All command and address input signals except CKE are SELF REFRESH COMMAND The SELF REFRESH command can be used to retain data "Don't Care" during self refresh.
in the DDR2 SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR2 SDRAM The procedure for exiting self refresh requires a sequence of retains data without external clocking. All power supply commands. First, the differential clock must be stable and meet inputs (including VREF) must be maintained at valid levels tCK specifications at least 1 x tCK prior to CKE going back HIGH. Once CKE is HIGH (tCLE(MIN) has been satisfied with upon entry/exit and during SELF REFRESH operation. four clock registrations), the DDR2 SDRAM must have NOP or The SELF REFRESH command is initiated like a REFRESH DESELECT commands issued for tXSNR because time is command except CKE is LOW. The DLL is automatically required for the completion of any internal refresh in progress. disabled upon entering self refresh and is automatically A simple algorithm for meeting both refresh and DLL enabled upon exiting self refresh (200 clock cycles must requirements is to apply NOP or DESELECT commands for then occur before a READ command can be 200 clock cycles before applying any other command.
Note: Self refresh not available at military temperature.
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RESET FUNCTION (CKE LOW Anytime)
DDR2 SDRAM applications may go into a reset state anytime during normal operation. If an application enters a reset condition, CKE is used to ensure the DDR2 SDRAM device resumes normal operation after reinitializing. All data will be lost during a reset condition; however, the DDR2 SDRAM device will continue to operate properly if the following conditions outlined in this section are satisfied. The reset condition defined here assumes all supply voltages (VDD, VDDQ and VREF) are stable and meet all DC specifications prior to, during, and after the RESET operation. All other input pins of the DDR2 SDRAM device are a "Don't Care" during RESET with the exception of CKE. If CKE asynchronously drops LOW during any valid operation (including a READ or WRITE burst), the memory controller must satisfy the timing parameter tDELAY before turning off the clocks. Stable clocks must exist at the CK, CK# inputs of the DRAM before CKE is raised HIGH, at which time the normal initialization sequence must occur. The DDR2 SDRAM device is now ready for normal operation after the initialization sequence.
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DC OPERATING CONDITIONS
Parameter Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage All Voltages referenced to Vss MIN Symbol VCC VCCQ VREF VTT 1.7 1.7 0.49 x VCCQ VREF - 0.04 TYP 1.8 1.8 0.50 x VCCQ VREF MAX 1.9 1.9 0.51 x VCCQ VREF + 0.04 Units V V V V Notes 1 4 2 3
1. V CCQ tracks V CC due to direct tie in package. 2. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed 2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 4. VCCQ tracks with VCC track with VCC.
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VCCQ VIN, VOUT TSTG TCASE Parameter Voltage on VCC pin relative to V SS Voltage on VCCQ pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Device Operating Temperature
ADDR, BAx RAS\, CAS\, WE\, CS\, CKE, DM, DQS, DQS\, RDQS CK, CK\ DM
Min -1.0 -0.5 -0.5 -55.0 -55.0 -8 -5 -5 -5 -5 -10
Max 2.3 2.3 2.3 125.0 125.0 8 5 5 5 5 10
Unit V V
o o
V C C
uA uA uA uA uA uA
II
Input Leakage current; Any input 0VIOZ IVREF
OV
VOUT
VDDQ, DQ & ODT Disabled
VREF Leakage Current
INPUT / OUTPUT CAPACITANCE
TA = 25oC, f = 1 MHz, VCC = VCCQ = 1.8V
Parameter Input capacitance (A0-A12, BA0-BA2, CS\, RAS\, CAS\, WE\, CKE, ODT) Input capacitance CK, CK# Input capacitance DM, DQS, DQS# Input capacitance DQ0-71 Symbol CADDR CIN2 CIN3 COUT Max 20 8 10 12 Unit pF pF pF pF
AS4DDR264M65PBG1 Rev. 0.5 06/08
Austin Semiconductor, Inc.
Austin, Texas
512.339.1188
www.austinsemiconductor.com
21
i PEM Gb 4.2 Gb SDRAM-DDR2 Austin Semiconductor, Inc. AS4DDR264M65PBG1
INPUT DC LOGIC LEVEL
All voltages referenced to Vss
Parameter Input High (Logic 1) Voltage Input Low (Logic 0) Voltage
Symbol VIH (DC) VIL (DC)
Min VREF + 0.125 -0.300
Max VCC + 0.3001 VREF - 0.125
Unit V V
Note 1: VCCQ = VCC, 300mV is allowed provided Vcc does not exceed 1.9V
INPUT AC LOGIC LEVEL
All voltages referenced to Vss
Parameter AC Input High (Logic 1) Voltage DDR2-400 & DDR2-533 AC Input High (Logic 1) Voltage DDR2-667 ACInput Low (Logic 0) Voltage DDR2-400 & DDR2-533 AC Input Low (Logic 0) Voltage DDR2-667 Symbol VIH (AC) VIH (AC) VIL (AC) VIL (AC) Min VREF + 0.250 VREF + 0.200 -0.3 -0.3 Max VCC+0.3001 VCC+0.3001 VREF - 0.250 VREF - 0.200 Unit V V V V
Note 1: VCCQ = VCC, 300mV is allowed provided Vcc does not exceed 1.9V
AS4DDR264M65PBG1 Rev. 0.5 06/08
Austin Semiconductor, Inc.
Austin, Texas
512.339.1188
www.austinsemiconductor.com
22
i PEM Gb 4.2 Gb SDRAM-DDR2 Austin Semiconductor, Inc. AS4DDR264M65PBG1
DDRII ICC SPECIFICATIONS AND CONDITIONS
Parameter Operating Current: One bank active-precharge tCL=tCK(ICC), tRC=tRC(ICC), tRAS=tRAS MIN(ICC); CKE is HIGH, CS\ is HIGH between valid commands; Address bus switching, Data bus switching Operating Current: One bank active-READ-precharge current IOUT=0ma; BL=4, CL=CL(ICC), AL=0; tCK = tCK(ICC), tRCtRC(ICC), tRAS=tRAS MIN(ICC), tRCD=tRCD(ICC); CKE is HIGH, CS\ is HIGH between valid commands; Address bus is switching; Data bus is switching Precharge POWER-DOWN current All banks idle; tCK-tCK(ICC); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet STANDBY current All banks idle; tCK=tCK(ICC); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge STANDBY current All banks idle; tCK-=tCK(ICC); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active POWER-DOWN current
MRS[12]=0
Symbol
667 MHZ -3
533 MHZ -38
400 MHZ -5
Units
ICC0
525
480
440
mA
ICC1
600
520
480
mA
ICC2P
30
30
30
mA
ICC2Q
250
210
160
mA
ICC2N
270
230
180
mA
125 ICC3P
105
95 mA
All banks open; tCK=tCK(ICC); CKE is LOW; Other control and address inputs are stable; Data bus inputs are floating Active STANDBY current
MRS[12]=1
40
40
40
All banks open; tCK=tCK(ICC), tRAS MAX(ICC), tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating Burst WRITE current All banks open, continuous burst writes; BL=4, CL=CL(ICC), tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH betwwn valid commands; Address bus inputs are switching; Data bus Operating Burst READ current All banks open, continuous burst READS, Iout=0mA; BL=4, CL=CL(ICC), AL=0; tCL=tCK(ICC), tRAS=tRAS MAX(ICC), tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH betwwn valid commands; Address and Data bus inputs switching Burst REFRESH current tCK=tCK(ICC); refresh command at every iRFC(ICC) interval; CKE is HIGH, CS\ is HIGH Between valid commands; Address bus inputs are switching; Data bus inputs are switching Self REFRESH current CK and CK\ at 0V; CKE AS4DDR264M65PBG1 Rev. 0.5 06/08
ICC3N
240
200
165
mA
ICC4W
685
565
485
mA
ICC4R
685
565
485
mA
ICC5
1000
880
800
mA
ICC6
30
30
30
mA
ICC7
1370
1280
1220
mA
Austin Semiconductor, Inc.
Austin, Texas
512.339.1188
www.austinsemiconductor.com
23
i PEM Gb 4.2 Gb SDRAM-DDR2 Austin Semiconductor, Inc. AS4DDR264M65PBG1
AC OPERATING SPECIFICATIONS
-3 333MHz/667Mbps MIN MAX 3 3.75 5 0.48 0.48
tCH,tCL
Parameter Clock Cycle Time CL=5 CL=4 CL=3 Clock High Time Clock Low Time Half Clock Period Clock Jitter - Period Clock Jitter - Half Period Clock Jitter - Cycle to Cycle Cumulative Jitter error, 2 Cycles Cumulative Jitter error, 4 Cycles Cumulative Jitter error, 6-10 Cycles Cumulative Jitter error, 11-50 Cycles DQ hold skew factor DQ output access time from CK/CK\ Data-out High-Z window from CK/CK\ DQS Low-Z window from CL/CK\ DQ Low-Z window from CK/CK\ DQ and DM input setup time relative to DQS DQ and DM input hold time relative to DQS DQ and DM input pulse width (for each input) Data Hold skew factor DQ-DQS Hold, DQS to first DQ to go non valid, per access Data valid output window (DVW) DQS input-high pulse width DQS input-low pulse width DQS output access time from CK/CK\ DQS falling edge to CK rising - setup time DQS falling edge from CK rising-hold time DQS-DQ skew, DQS to last DQ valid, per group, per access DQS READ preamble DQS READ postamble WRITE preamble setup time DQS WRITE preamble DQS WRITE postamble Positive DQS latching edge to associated Clock edge WRITE command to first DQS latching transition Min of
Symbol tCKAVG tCKAVG tCKAVG tCHAVG tCLAVG tHP tJIT PER tJIT DUTY tJIT CC tERR2PER tERR4PER tERR10PER tERR50PER tQHS tAC tHZ tLZ1 tLZ2 tDSJEDEC tDHJEDEC tDIPW tQHS tQH tDVW tDQSH tDQSL tDQSCK tDSS tDSH tDQSQ tRPRE tRPST tWPRES tWPRE tWPST tDQSS
-38 266MHz/533Mbps MIN MAX 3.75 5 0.48 0.48
tCH,tCL
-5 200MHz/400Mbps MIN MAX 5 5 0.48 0.48
tCH,tCL
Units ns ns ns tCK tCK ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps tCK ps ps ps tCK tCK ps tCK tCK ps tCK tCK ps tCK tCK tCK tCK
8 8 8 0.52 0.52 125 125 250 175 250 350 450 340 450
tAC(MAX) tAC(MAX) tAC(MAX)
8 8 0.52 0.52 125 125 250 175 250 350 450 400 500
tAC(MAX) tAC(MAX) tAC(MAX)
8 8 0.52 0.52 125 150 250 175 250 350 450 450 600
tAC(MAX) tAC(MAX) tAC(MAX)
-125 -125 -175 -250 -350 -450 -450
tAC(MIN) 2*tAC(MIN)
-125 -125 -175 -250 -350 -450 -500
tAC(MIN) 2*tAC(MIN)
-125 -150 -175 -250 -350 -450 -600
tAC(MIN) 2*tAC(MIN)
100 175 0.35 340
tHP-tQHS tQH-tDQSQ
100 225 0.35 400
tHP-tQHS tQH-tDQSQ
150 275 0.35 450
tHP-tQHS tQH-tDQSQ
0.35 0.35 -400 0.2 0.2 0.9 0.4 0 0.35 0.4 -0.25
400
0.35 0.35 -400 0.2 0.2 0.9 0.4 0 0.35 0.4 -0.25
400
0.35 0.35 -450 0.2 0.2 0.9 0.4 0 0.35 0.4 -0.25
450
240 1.1 0.6
300 1.1 0.6
350 1.1 0.6
0.6 0.25
0.6 0.25
0.6 0.25
WL-tDQSS WL+tDQSS WL-tDQSS WL+tDQSS WL-tDQSS WL+tDQSS
AS4DDR264M65PBG1 Rev. 0.5 06/08
Austin Semiconductor, Inc.
Austin, Texas
512.339.1188
www.austinsemiconductor.com
24
i PEM Gb 4.2 Gb SDRAM-DDR2 Austin Semiconductor, Inc. AS4DDR264M65PBG1
AC OPERATING SPECIFICATIONS (CONTINUED)
-3 333MHz/667Mbps MIN MAX 0.6 200 275 2 55 10 15 50 40 7.5 15
tWR + tRP
Parameter Address and Control input puslse width for each input Address and Control input setup time Address and Control input hold time CAS\ to CAS\ command delay ACTIVE to ACTIVE command (same bank) ACTIVE bank a to ACTIVE bank b Command ACTIVE to READ or WRITE delay 4-Bank activate period ACTIVE to PRECHARGE Internal READ to PRECHARGE command delay WRITE recovery time Auto PRECHARGE WRITE recovery+PRECHARGE time Internal WRITE to READ command delay PRECHARGE command period PRECHARGE ALL command period LOAD MODE, command Cycle time CKE LOW to CK, CK\ uncertainty REFRESH to ACTIVE or REFRESH to REFRESH command Interval Average periodic REFRESH interval [Industrial temp] Average periodic REFRESH interval [Enhanced temp] Average periodic REFRESH interval [Extended temp] Exit SELF REFRESH to non READ command Exit SELF REFRESH to READ command Exit SELF REFRESH timing reference ODT turn-on delay ODT turn-on delay ODT turn-off delay ODT turn-off delay
Symbol tIPW tISJEDEC tIHJEDEC tCCD tRC tRRD tRCD tFAW tRAS tRTP tWR tDAL tWTR tRP tRPA tMRD tDELAY tRFC tREFIIT tREFIET tREFIXT tXSNR tXSRD tISXR tAOND tAOND tAOPD tAOF tAONPD tAOFPD tANPD tAXPD tMOD tXARD tSARDS tXP tCLE
-38 266MHz/533Mbps MIN MAX 0.6 250 375 2 55 10 15 50 40 7.5 15
tWR + tRP
-5 200MHz/400Mbps MIN MAX 0.6 350 475 2 55 10 15 50 40 7.5 15
tWR + tRP
Units tCK ps ps tCK ns ns ns ns ns ns ns ns ns ns ns tCK ns ns us us us ns tCK ps
COMMAND and ADDRESS
700001
700001
700001
7.5 15
tRP+tCL
7.5 15
tRP+tCL
10 15
tRP+tCL
2
tIS + tCL + tIH
2
tIS + tCL + tIH
2
tIS + tCL + tIH
REFRESH
127
70000 1 7.8 5.9 3.9
127
70000 1 7.8 5.9 3.9
127
70000 1 7.8 5.9 3.9
S. REFRESH
tRFC(min)+ 10
tRFC(min)+ 10
tRFC(min)+ 10
200 tIS 2
tAC(min)
200 tIS 2
tAC(max)+ 700
200 tIS 2
tAC(max)+ 1000
2
tAC(min)
2
tAC(min)
2
tAC(max)+ 1000
tCK ps tCK ps ps ps tCK tCK ns tCK tCK tCK tCK
2.5
tAC(min) tAC(min) + 2000 tAC(min) + 2000
2.5
tAC(max)+ 600 2 x tCK + tAC(max)+ 1000 2.5 x tCK + tAC(max)+ 1000
2.5
tAC(min) tAC(min) + 2000 tAC(min) + 2000
2.5
tAC(max)+ 600 2 x tCK + tAC(max)+ 1000 2.5 x tCK + tAC(max)+ 1000
2.5
tAC(min) tAC(min) + 2000 tAC(min) + 2000
2.5
tAC(max)+ 600 2 x tCK + tAC(max)+ 1000 2.5 x tCK + tAC(max)+ 1000
ODT
ODT turn-on (power-down mode) ODT turn-off (power-down mode) ODT to power-down entry latency ODT power-down exit latency ODT enable from MRS command Exit active POWER-DOWN to READ command, MR[12]=0 Exit active POWER-DOWN to READ command, MR[12]=1 Exit PRECHARGE POWER-DOWN to any non READ CKE Min. HIGH/LOW time
PWRDN
3 8 12 2
7 - AL
3 8 12 2
6 - AL
3 8 12 2
6 - AL
2 3
2 3
2 3
o Note 1: Max value reduced to 10,000ns at 125 C
AS4DDR264M65PBG1 Rev. 0.5 06/08
Austin Semiconductor, Inc.
Austin, Texas
512.339.1188
www.austinsemiconductor.com
25
i PEM Gb 4.2 Gb SDRAM-DDR2 Austin Semiconductor, Inc. AS4DDR264M65PBG1
MECHANICAL DIAGRAM
208 x O 0.60 (0.024) NOM 11 10 9 8 7 6 5 4 3 2 1
A B C D E F G
24.15 (0.951) MAX
18.0 (0.709) NOM
H J K L 2.
1.0 (0.039) NOM
M N P R T U V W
1.0 (0.039)NOM 0.50 (0.020) NOM 10.0 (0.394) NOM
16.15 (0.636) MAX
2.00 (0.079) MAX
AS4DDR264M65PBG1 Rev. 0.5 06/08
Austin Semiconductor, Inc.
Austin, Texas
512.339.1188
www.austinsemiconductor.com
26
i PEM Gb 4.2 Gb SDRAM-DDR2 Austin Semiconductor, Inc. AS4DDR264M65PBG1
ORDERING INFORMATION
Part Number AS4DDR264M65PBG1-3/IT AS4DDR264M65PBG1-38/IT AS4DDR264M65PBG1-5/IT AS4DDR264M65PBG1-3/ET AS4DDR264M65PBG1-38/ET AS4DDR264M65PBG1-5/ET AS4DDR264M65PBG1-3/XT AS4DDR264M65PBG1-38/XT AS4DDR264M65PBG1-5/XT AS4DDR264M65PBG1R-3/IT AS4DDR264M65PBG1R-38/IT AS4DDR264M65PBG1R-5/IT AS4DDR264M65PBG1R-3/ET AS4DDR264M65PBG1R-38/ET AS4DDR264M65PBG1R-5/ET AS4DDR264M65PBG1R-3/XT AS4DDR264M65PBG1R-38/XT AS4DDR264M65PBG1R-5/XT Core Freqency 333MHz 266MHz 200MHZ 333MHz 266MHz 200MHZ 333MHz 266MHz 200MHZ 333MHz 266MHz 200MHZ 333MHz 266MHz 200MHZ 333MHz 266MHz 200MHZ Data Rate 667Mbps 533Mbps 400Mbps 667Mbps 533Mbps 400Mbps 667Mbps 533Mbps 400Mbps 667Mbps 533Mbps 400Mbps 667Mbps 533Mbps 400Mbps 667Mbps 533Mbps 400Mbps Device Grade Industrial Industrial Industrial Enhanced Enhanced Enhanced Extended (Mil-Temp) Extended (Mil-Temp) Extended (Mil-Temp) Industrial - RoHS Industrial - RoHS Industrial - RoHS Enhanced - RoHS Enhanced - RoHS Enhanced - RoHS Extended - RoHS Extended - RoHS Extended - RoHS Availability Consult Factory Consult Factory Consult Factory Consult Factory Consult Factory Consult Factory Consult Factory Consult Factory Consult Factory Consult Factory Consult Factory Consult Factory Consult Factory Consult Factory Consult Factory Consult Factory Consult Factory Consult Factory
IT = Industrial = Industrial class integrated component, fully operable across -40C to +85C ET = Enhanced = Enhanced class integrated component, fully operable across -40C to +105C XT = Extended = Mil-Temperature class integrated component, fully operable across -55C to +125C
AS4DDR264M65PBG1 Rev. 0.5 06/08
Austin Semiconductor, Inc.
Austin, Texas
512.339.1188
www.austinsemiconductor.com
27
i PEM Gb 4.2 Gb SDRAM-DDR2 Austin Semiconductor, Inc. AS4DDR264M65PBG1
DOCUMENT TITLE 4.2Gb, 64M x 64, DDR2 SDRAM, 16mm x 23mm - 208 PBGA Multi-Chip Package [iPEM] REVISION HISTORY Rev # 0.0 0.5 History Initial Release Updated Pinout & Pin Desc Release Date May 2008 June 2008 Status Advance Advance
AS4DDR264M65PBG1 Rev. 0.5 06/08
Austin Semiconductor, Inc.
Austin, Texas
512.339.1188
www.austinsemiconductor.com
28

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